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  • ​Reliable analog and mixed-signal circuit design
    • Design approaches to reduce circuit degradation and optimize analog and mixed-signal circuit design for reliability
    • Significantly narrowed reliability safety margin resulting from the aggressive feature size scaling of contemporary VLSI circuits into sub-micron range
    • Trade-off between reliability margins and performance of analog circuits
    • Modeling reliability, variability, and crosstalk that define presilicon design methodology and trends
  • Digitally-assisted analog circuits

    • Development of efficient methods to move analog into digital domain quickly, minimizing and eliminating common trade-offs between performance, power consumption, simulation time, verification, size, and cost

  • Low-distortion and low-noise circuits

    • Approaches for very low-power and low-noise performances for high-speed interfaces, phase-locked loops (PLLs), voltage-controlled oscillators (VCOs), analog-to-digital converters (ADCs), and analog filters

  • High-speed I/O design for testing

    • Characterization system design for EPHY/GPHY, 10GbE, 40GbE, and 16-nm process Ethernet multilayer controller with 25-Gbps SerDes cores

    • BIST-based eye margin test methodology development

    • Design of characterization system for high-precision analog and mixed-signal IP cores embedded in MEMS-based motion-sensor SoCs

    • Prediction systems for static and dynamic performances of ultra-high-speed GHz DACs

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